In a virtual memory digital data processing system a central processing unit (CPU) issues virtual memory addresses which are translated into real, or physical, memory addresses. Such a virtual memory system typically comprises a physical memory such as random access memory (RAM) typically having a number of storage locations less than the address capability of the CPU. The virtual memory system also typically comprises a mass storage system such as a magnetic disk or tape having a storage capacity which typically far exceeds that of the physical memory size, and also a virtual memory control mechanism. The virtual memory control mechanism typically comprises circuitry adapted for translating a CPU generated virtual address into a physical memory address, circuitry adapted for determining if the data addressed by the CPU is currently resident in the physical memory and circuitry adapted for suspending a CPU access until the desired data can be retrieved from the mass storage device and stored in the physical memory. Data retrieved from the mass storage device and stored in physical memory may also be subsequentially rerecorded within the mass storage device. The data transferred between mass storage and physical memory is typically organized into blocks of data having, for a particular data processing system, a predetermined format. One format is that of a variable data length segment. Another format is that of a fixed data length page. A still further format is a hybrid segment/page type of data block.
In any type of virtual memory data processing system a desired feature is that the limited and valuable resources of the physical memory be efficiently utilized. Inasmuch as a CPU access to data resident in physical memory may occur at least an order of magnitude faster than an access to data which is not resident in physical memory and which must therefore be retrieved from the mass storage device, it can be appreciated that the continued residency of appropriate data within the physical memory is a important concern. Another important concern is that data which is modified by the CPU, while resident in physical memory, be accurately rerecorded into the mass storage device. In order to accomplish these important goals it has been known to provide the virtual memory control mechanism with circuitry adapted for recording both the occurrence of a CPU access to a particular block of data in physical memory and also whether the data was modified by a write type of access. Such circuitry may be referred to as a reference and change table (RCT) and typically comprises a memory device having a predetermined number of storage locations for recording the occurrence of a CPU access to a particular data block and whether the access was a write type of access.
One particular problem with conventional RCTs is that they are embodied in a single logical element or a plurality of logical elements and are typically disposed within the virtual memory control system. These centralized RCTs typically have a fixed storage capacity which may represent a storage capacity substantially equal to the maximum virtual address capability of the CPU. For example, if the CPU has 24 address bits, the upper eight bits may define a particular page of data within virtual memory while the lower 16 bits may represent an index into the page of virtual memory. Such a CPU would therefore have a virtual memory space organized as 256 pages each comprising 65,536 memory locations. The RCT would consequently be required to have, for example, 256 memory locations (one for each page). However, if the data processing system only has the equivalent of 16 pages of physical memory installed, it can be appreciated that additional system cost, represented at least by the unused capacity of the RCT, has been needless incurred. Inasmuch as many modern CPUs, which typically comprise a microprocessor device, have a virtual memory addressing capability of hundreds of megabytes of data or more, the required storage capacity of an associated centralized RCT may be unacceptably large. Even if, for a given system, the RCT has a fixed, smaller storage capacity than the maximum virtual memory address capability of the CPU the RCT capacity may still need to be made larger than necessary in order to accommodate projected increases in system memory capacity. The fixed storage capacity of such a reduced capacity RCT may then substantially prove disadvantageous if it is desired to increase the system storage capacity beyond the originally designed capacity, such as by attaching additional memory modules to the system. The fixed size of the RCT thus imposes a maximum limit on the virtual and physical memory space of the system.
It is therefore one object of the invention to provide a system RCT of variable storage capacity.
It is a further object of the invention to provide a modular RCT which is physically distributed throughout the physical memory space of a virtual memory data processing system.
It is one still further object of the invention to provide a modular, distributed RCT for a virtual memory data processing system which readily accommodates the expansion of the virtual memory space up to the maximum addressing capability of the data processing system CPU.
It is also an object of the invention to provide a memory module adapted for being attached to a virtual memory data processing system which comprises an integral RCT having a storage capacity equal to the number of virtual memory data blocks which may be stored within the memory module.
It is a still further object of the invention to provide a memory carrier module adapted for being coupled to a virtual memory data processing system and having one or more memory modules disposed thereon, each of the memory modules having an integral RCT.